The Next-Generation Wafer
Semiconductor devices are required to achieve simultaneous improvements in packing density, performance and economic rationality. These cannot be done without enhancing the quality of silicon wafers in terms of cleanliness, flatness and other characteristics. While wafer size growth increases handling difficulty in the manufacturing process, SUMCO has accomplished a number of technical innovations.
Silicon wafer manufacturing processes
Technical innovations in progress
A breakthrough in the mono-crystalline silicon pulling process
A larger wafer size means that the weight of a mono-crystalline silicon ingot manufactured increases and it takes longer time to pull and cool the ingots. It is therefore difficult to constantly produce high quality crystals.
SUMCO has established a sophisticated manufacturing process optimized for 300 mm wafers in terms of supporting high weights and controlling crystal quality.
A breakthrough in creating an ultra-clean manufacturing environment
All silicon wafer manufacturing processes take place in a clean room where a high degree of cleanliness is maintained.
Moreover, SUMCO has introduced a mini-environment technology to locally clean the space where wafers are exposed. A wafer carrier referred to as the Front Opening Unified Pod (FOUP) is used for inter-process transfer during wafer production. This technology ensures that wafers are automatically transferred to a subsequent process without manual human intervention in a hermetically sealed, clean room environment.
A breakthrough in silicon wafer quality
In the wafer polishing process, SUMCO uses a double-sided polishing technology. This method performs polishing simultaneously on both sides of the wafer at an even pressure to create uniform surface conditions and a higher degree of flatness.
Wafer transfer within the process utilizes a handling system that grips the wafer at its edge to improve surface cleanliness. Contamination or physical damage on the rear of the wafer is less likely than it is with conventional backside handling.
As explained above, silicon wafer manufacturing technologies were radically re-engineered in order to achieve the innovation necessary to increase the wafer size from 200 to 300 mm.
What if the diameter is increased another 50% to 450 mm? Many difficulties are likely to arise in constructing an optimal manufacturing line for 450 mm wafers, if the technical innovations for 300 mm production are merely extended.
