The Next-Generation Wafer

The performance of semiconductor devices requires the miniaturization of circuit line widths with the use of nanotechnology. This increases the density in IC chips to create a broad array of high-performance devices, such as ULSI (Ultra Large Scale Integration) products.

One nanometer is equivalent to one billionth of a meter. Silicon wafers, serving as the foundation in the world of nano-scale semiconductor devices, need to have a near-zero deficiency in flatness and cleanliness.

In the near future, the circuit line widths in semiconductor devices will fall to within a range of 10 - 20 nm. As a consequence, a tightening of quality requirements for silicon wafers will be unavoidable.

What needs to be done to meet such requirements with 450 mm wafers? There are several challenges that the industry must discuss and overcome if it is to manufacture wafers with a quality higher than the 300 mm model. These include innovations in the technologies for manufacturing mono-crystalline silicon ingots, wafer processing and verification of the mechanical characteristics of silicon wafers.

Anticipating the coming era of 450 mm wafers, SUMCO quickly embarked on basic research and small-scale prototyping efforts. In the next edition, data obtained from the process of testing new technologies will be published on this website. We hope you will be sure to take a look.