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SUMCO provides high-quality silicon wafers supporting the semiconductor industry at the leading edge. Raw materials with the highest level of quality are used as the silicon wafer material. The wafers are produced under the strictest quality control to create products meeting customer needs in all kinds of ways.

Ultra-flat, ultra-clean wafers produced under strict quality control

Polished Wafer (PW)

A monocrystalline ingot is sliced to thicknesses of around 1mm and the surfaces are polished to a mirror finish. As a result, the wafers are exceptionally flat and clean.
SUMCO can also add gettering capability to the wafer, by which heavy metal impurities that can degrade electrical properties are captured.

Wafers with a vapor phase growth layer of monocrystalline silicon

Epitaxial Wafer (EW)

For superior quality, the surface layer of the polished wafer is formed from monocrystalline silicon using vapor phase growth, or epitaxy.

Cross-sectional diagram of an epitaxial wafer, illustrating the two-layer structure consisting of an epitaxial growth layer on a polished wafer (PW) substrate.

Wafers with improved surface crystal perfection thanks to high-temperature annealing

Annealed Wafer (AW)

A polished wafer undergoes high-temperature annealing in an atmosphere of hydrogen or argon, removing oxygen near the wafer surface.The resulting wafer features a modified surface layer with improved crystal perfection.

Cross-sectional diagram of an annealed wafer showing a two-layer structure: a surface modified layer and a Polished Wafer (PW) substrate.

Wafers with a layer for embedding integrated circuits

Junction Isolated Wafer (JIW)

First the customer’s design is followed to form an embedding layer for integrated circuits on the surface of the wafer employing photolithography, ion implantation, and thermal diffusion techniques. An epitaxial layer is then formed on top of this layer.

Cross-sectional diagram of an epitaxial wafer with buried layers, illustrating a three-layer structure: an epitaxial growth layer on top, partially embedded IC layers in the middle, and a polished wafer substrate at the base.

Wafers with an oxide layer under the active layer for higher integration

Silicon-On-Insulator (SOI) Wafer

An oxide layer with high electric insulation is sandwiched between two polished wafers, which are then bonded together. This enables devices with high integration, low power consumption, high speed, and high reliability. A diffusion layer of arsenic (As) or antimony (Sb) can also be formed in the active layer at the wafer surface.

Cross-sectional diagram of an SOI wafer illustrating its three-layer structure: the top active layer, the middle oxide layer, and the base polished wafer substrate.

Recycled wafers created by removing customer device layers

Reclaimed Polished Wafer (RPW)

On customer request, used wafers can be taken back and recycled for reuse.

Overview diagram of reclaimed wafers. It illustrates the process where the device layer of a used wafer is removed and then polished/reprocessed to create a reclaimed wafer.